A structure in which a semiconductor chip is mounted face down onto a wiring board or onto another semiconductor chip and in which their electrodes are connected to each other via a bump electrode has been conventionally known as a connection structure between a semiconductor chip and a substrate or between semiconductor chips.
In semiconductor devices having such connection structure, efforts have been made in recent years to miniaturize the bump electrodes which are to be formed on a semiconductor chip, etc., and to reduce the chip pitch, in order to meet the needs for smaller and thinner mobile phones, etc. This has consequently created a necessity in which, when a semiconductor chip and a substrate, etc., are to be connected to each other, they have to be aligned with high accuracy in order to securely connect the corresponding bump electrodes thereof. For example, the width of bump electrodes that is predominantly employed these days is 10 μm or less, and the required accuracy of alignment is 1 μm or less.
In order to achieve a highly accurate alignment, Patent Document 1 describes forming a recess having an inner lateral surface defining a conical shape in one of the electrodes. In such configuration, even if the positions of this recess and the other electrode (bump electrode) are slightly out of alignment, the bump electrode can still be guided so as to be slid along the inner lateral surface of the recess during the process of bringing these electrodes closer to each other. As a result, the central axis of the bump electrode and the central axis of the recess can be easily caused to coincide with each other, thereby achieving a highly accurate alignment.
After performing the alignment, the electrodes have to be joined. Various methods of joining electrodes are known, examples of which include pressure welding, solder joining and ultrasonic joining. Of these joining methods, ultrasonic joining causes a small amount of stress on semiconductor chips, etc., with a relatively small load and relatively small temperature rise during joining, and it is therefore the most preferable method for compound semiconductor chips such as GaAs, InP, CdTe, ZnSe, AlGaAs, InGaAs, GaInNAs and for Si semiconductor chips fabricated to have a thin thickness of 20-100 μm.